A typical three-dimensional n-well CMOS inverter structure studied in this work is shown in Fig. 1. The device is established based on 0.35-μm CMOS technology and the distance between two gates is 5 μm. The device has 10.5 μm of total lateral size and 4 μm of depth, 2 μm of the vertical length of n-well. Arsenic and Boron are chosen to create n-type and p-type doped regions. Two parasitic transistors Q₁ and Q₂ are exhibited in the schematic diagram, the impedances of substrates are represented by r_well and r_sub respectively. Under normal operation conditions, the supply voltage V_dd is 3.3 V with mid-point voltage V_m located at about 1.65 V. The initial temperature of the device is 300 K to meet the ambient temperature, and the top surface is set to be adiabatic. The logic flip function of CMOS inverter is realized through V_in and V_out. An EMI is injected into V_in directly to simulate the unprotected inputs in CMOS circuits. The injected plane wave is in sinusoidal form which is proved to be convictive in experiment.^[24] The power of the EMI ranges from 3 dBm to 32 dBm, and the interference frequency is focused on 1 GHz to 5 GHz (L to C waveband). These conditions are appropriate to the inducing of the soft logic upset in CMOS inverters after adequate attempts.

Fig. 1.

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	Fig. 1. Schematic diagram of n-well CMOS inverter structure.

The latch-up effect is considered to be one of the upset mechanisms in CMOS inverters.^[12–17] However, when the EMI is not severe enough to trigger the latch-up, the interference on CMOS inverters will induce a real-time soft logic upset. To thoroughly understand the physical mechanism of this upset, we begin with the semiconductor continuity equation in CMOS inverter under the thermal equilibrium state 1 where n₀ and p₀ refer to the initial electron concentration and the initial hole concentration, G₀ is the generation rate, R₀ = n₀p_0r is the recombination rate, and r is the probability of electron hole recombination. When the sinusoidal EMI signal V_in is injected, the external EMI produces an interference electric field immediately in both gates of the inverter. Since the field strength is not strong enough to cause an oxide breakdown, the generation rate under EMI remains invariable. So the continuity equation under EMI is given as 2 in which n_EMI and p_EMI are the interfered electron concentration and the interfered hole concentration, respectively; r′ is the influenced probability of recombination.

In practical applications, CMOS inverter often works in the state that one of the MOSFETs is on and the other is off. So here we illustrate a condition that V_in = 3.3 V (input logic high) to help analyze the EMI process. In this circumstance, non-equilibrium carriers are evoked in both positive channel metal–oxide–semiconductor (PMOS) and negative channel metal–oxide–semiconductor (NMOS) substrates and then swept into the channels to influence the conductive character of the device. In the NMOS part of the inverter, the existence of the inherent inversion channel current cannot obviously change its conductivity when the non-equilibrium electrons arrive at the channel. In the PMOS part, an extra channel current is generated by the non-equilibrium holes and becomes the main reason to induce the soft logic upset. A schematic diagram of a whole interfering period at PMOS when V_in = 3.3 V can be seen in Fig. 2. The injection sinusoidal EMI signal V_i is spilt into four parts according to its variation tendency. In the first part, shown in Fig. 2(a), V_i > 0 and ∂V_i/∂ t > 0, which means the growing interference field is along the y axis, pushing the non-equilibrium electrons to the channel. However, no lateral channel current arises since the source and drain of the PMOS are in p-type doping. During the second part in Fig. 2(b), V_i > 0 and ∂V_i/∂ t < 0, so the channel current remains negligible and the accumulation of non-equilibrium electrons decreases. The third part is illustrated in Fig. 2(c), the interference field changes its orientation and moves the non-equilibrium holes to the channel. During this part, the extra channel inversion layer current appears and increases with the strength of the interference field increasing, leading to a soft upset in the inverter. In the fourth part as seen in Fig. 2(d), the extra channel current falls down with the decrease of interference field, meanwhile the upset to the logic features mitigates.

Fig. 2.

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	Fig. 2. Schematic diagram of the generation and transportation of non-equilibrium carriers in inverter’s PMOS during a whole interference period.

Considering no direct injection of non-equilibrium carriers occurring during the soft logic upset (because no oxide breakdown happens), the generation of non-equilibrium carriers is attributed to the change of the electron–hole recombination probability r. As is well known, the generation and recombination happen constantly in a doped semiconductor. When the EMI appears, part of generated carriers are swept away (along or against the field direction) before their recombination, leading the electron hole recombination probability r to decrease. The recombination probability change in PMOS can be expressed as follows: 3 where is the EMI affected recombination probability in PMOS substrate, f is the frequency of EMI signal, and φ is its initial phase, and t is the interference time. The EMI induced extra non-equilibrium holes Δp = p_EMI − p₀. Since the inverter is in thermal equilibrium, ∂p₀/∂ t = 0, we have ∂ Δ p/∂ t = ∂ p_EMI/∂ t. Meanwhile, under the slowly and continuously varying EMI signal, ∂ p_EMI/∂ t = 0. Additionally, the non-equilibrium carriers are formed in pairs, so ∂ Δ p = ∂ Δn. Substituting these conditions into Eq. (2), the extra non-equilibrium holes Δp can be calculated from 4 and the accumulation of the non-equilibrium holes in PMOS channel will inevitably form an extra channel current. Based on the semiconductor current density equation, the PMOS extra channel current density can be shown as follows: 5 where q is the charge energy, μ_p is the hole mobility, d_ox and T respectively are the thickness of gate oxide layer and the channel depth, V_EMI is the virtual value of external interference voltage, and D_p is the hole diffusion coefficient. The diffusion current under EMI is along the y axis, which barely contributes to the extra channel current, so we have qD_p(∂ p_EMI/∂ y) ≈ 0. Then the PMOS extra channel current can be expressed as 6 where L is the channel length. As the interference field increases, a peculiar situation occurs that the drift speed along the negative y axis is much higher than along the x axis, leading some non-equilibrium carriers to collide with each other in the surface of gate oxide and substrate. The H(P^EMI) is used here to explain this kind of extra current loss, where P^EMI is the power of the injection EMI signal.

Similarly, when V_dd = 0 V, the soft logic upset is mainly determined by the interference in the NMOS channel, the extra channel current I_extra-n can be calculated from 7 The minority carriers in the substrate of NMOS are electrons, so the I_extra-n occurs in the first half of each disturbance cycle as exhibited in Fig. 2. Furthermore, the EMI induced output logic deviations can be calculated respectively based on the I_extra-p and I_extra-n, and are expressed as 8 9 where ΔV_high and ΔV_low are the deviation of output high level and output low level, W is the channel width, V_G and V_T are the gate voltage and threshold voltage in normal operation condition, and C_ox is the inherent capacitance of the gate oxide layer.

The voltage transfer characteristic (VTC) curve under EMI induced soft logic upset is revealed in principle in Fig. 3. Figure 3(a) shows the I_D–V_out curves of NMOS and PMOS in the inverter. It is easy to notice that when V_in = 0 V, the EMI induced I_extra-n changes the intersection point between the NMOS and PMOS load lines from A to B, and causes a V_out to shift by ΔV₁, which eventually leads to the decrease from V_OH to in the VTC curve as seen in Fig. 3(b). Identically, the I_extra-p induces a change from C to D, which evokes the ΔV₂ and the VTC curve deviating from V_OL to . For the same reason, the I_extra-p and I_extra-n can influence the whole VTC curve of the CMOS inverter. One thing should be noticed is that the turned-on MOSFST shows some current loss in its saturation region (seen in two dotted regions in Fig. 3(a)). The reason of this phenomenon is that the strong interference field on the gate of the non-sensitive MOSFET (for example, the NMOS when V_in = 3.3 V) pushes some inverse carriers to the substrate, which is not the dominant cause of the soft logic upset. According to the deduction above, the soft logic upset can be more intuitively demonstrated by the decay of static characteristics. Moreover, the recession of the output range, gain and a noise margin can be noticed easily in the curve as well.

Fig. 3.

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	Fig. 3. (color online) Schematic diagram of soft logic upset principle through a deviation of the voltage transfer characteristic (VTC) curve.

Figure 4 indicates the numerical simulation output voltages of the CMOS inverter. The EMI signal V_in’s ranging from 3 dBm to 32 dBm in value are applied in the time range from 5 ns to 10 ns (to save simulation time, no cumulative effect is found in longer term simulation attempt). The EMI is superposed with the original input logic level which is low in Fig. 4(a) and high in Fig. 4(b). A time-dependent output deviation is observed which fits the soft logic upset features well. Moreover, when V_in = 3.3 V, the upset occurs in second half of each EMI cycle, which is in line with the analyzed results mentioned in Subsection 2.2, and the disturbed output voltages are also in sinusoid-like form and increase with the augment of the injection power. The same consequence is also shown in Fig. 4(a).

Fig. 4.

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	Fig. 4. (color online) Numerical simulation output voltages varying with time under 3 dBm to 32 dBm EMI Vin = 3.3 V (a) and 0.0 V (b).

The jumping interference output voltages in Fig. 4 are intuitional but hard to measure accurately. Wang et al. reported that a duplexer was used in EMI injection experiments.^[20] The interference output voltages can be separated into upset output logic voltages and high frequency clutters. Referencing this idea, a digital filter module is introduced in simulation as shown in Fig. 5. The numerical simulation output voltage data (for example, one of the curves in Fig. 4) is imported in the input voltage A, which can be observed directly in oscilloscope 1. Oscilloscopes 2 and 3 show the high frequency clutter and the upset output logic voltage respectively by sending the input voltage A into the high-pass and low-pass filters. The data output retains the useful upset output logic voltage data in an array named Simout. Using this method, it is easy to visualize the EMI induced soft logic upset through an output logic deviation. Figure 6 shows the comparison between the processed simulation output logic voltages (seen in Fig. 6(b)) and experimental results (seen in Fig. 6(a)) reported in Ref. [20]. The input levels are both low, and the frequencies of EMI are 1 GHz identically. Fine conformity of their trends can be noticed between experiments and simulations, the difference in specific value is caused by the actual experimental equipment loss and the difference between simulated and real manufactured inverters. Considering the original features of the digital filter, there is a filter delay of about 3 ns as shown in Fig. 6(b), which barely affects the tendency of the curves. Based on the simulation results, an experiment measurable parameter ΔV marked in Fig. 6(b) is used to estimate degree of soft logic upset in this work, which is expressed as 10 where is the filtered output logic voltage under EMI and V_out is the normal output level.

Fig. 5.

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	Fig. 5. Schematic diagram of digital filter module.

Fig. 6.

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	Fig. 6. (color online) Upset logic output voltages in (a) experiments reported in Ref. [20], (b) simulations after using the digital filter module.

Mechanism explanation in Subsection 2.2 reveals that the extra channel current induces the soft logic upset in CMOS inverter. To justify the proposed parameter ΔV, in Fig. 7 we plot the curves of ΔV and the interfered extra channel current density J_extra (including J_extra-n and J_extra-p) versus injected interference power. A parallel rising tendency between ΔV and J_extra emerges with the increase of the EMI injection power, indicating that the parameter ΔV can reflect the channel carrier distribution changes in CMOS inverters reasonably.

Fig. 7.

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	Fig. 7. (color online) Curves of ΔV and interference extra channel current density Jextra-n and Jextra-p versus injected interference power.

The experimentally measurable parameter ΔV describes the soft logic upset conveniently. However, to comprehensively measure the device situation under soft logic upset, an extraction of the voltage transfer characteristic is helpful. To achieve this, a carrier equivalent simulation method is used in this work. Based on above-mentioned study, 5 groups of data (N_pn, T) (Here, N_pn (n = 1, 2, 3, 4, 5) is the peak doping concentration and T is the thickness of the interference extra carrier layer.) are collected in numerical simulation results at the positions that make the channel 5 equal parts, the collecting time points are the ends of the first and third parts of one interference cycle. Then the equivalent interference carrier doping concentration C_s is given as 11 where H(P^EMI) ≈ 1/2 when injection power is lower than 30 dBm and H(P^EMI) ≈ 1/4 when higher than 30 dBm according to previous simulations. Figure 8 reveals the variations of C_s and T with the increase of injected voltage. An approximately proportional relationship between C_s and interference voltage can be found, meanwhile the interference extra carrier layer thickness T is found to be almost stable at 10 nm in both MOSFETs. Then we remodel the device by using the data in Fig. 8, two man-made inversion channels are placed into the simulation structure. Using this carrier equivalent simulation method, complete VTC curves under augmented EMI can be obtained. The contrast between the EMI induced inverter VTC degradation in simulation and that in reported experimental results^[19] can be seen in Fig. 9. Besides good consistency between simulations (seen in Fig. 9(a)) and experiments (seen in Fig. 9(b)), several signs of degradation in static performance of the inverter can be observed likewise. Besides the decrease of output logic voltage range V_OH − V_OL, the attenuation of gain (g_m = ∂I_ds/∂ g_s) and the degeneration of noise margin SNM_H and SNM_L (SNM_H = V_OH − V_IH and SNM_L = V_IL − V_OL) are also observed. All these phenomena are supported by the mechanism in Subsection 2.2. Furthermore, with the increase of the EMI power, the degradation of VTC curves becomes more severe. When the injection power reaches 20 dBm, the VTC curve comes to a complete recession, which means the disappearing of the flip feature in CMOS inverter. In addition, since the simulations are under ideal conditions and the device size and supply voltage in simulation are different from in experiment, the interference VTC curves cannot be exactly the same.

Fig. 8.

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	Fig. 8. (color online) Variations of equivalent interference carrier doping concentration Cs and average channel depth T with injection voltage increasing.

Fig. 9.

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	Fig. 9. (color online) Comparisons of EMI-induced inverter’s VTC degradation between (a) simulation results and (b) experimental results reported in Ref. [19].

To verify the simulation model more comprehensively, experiments can be setup as shown in Fig. 10. The interference signal V_EMI is generated by a network analyzer (e.g., HP8753C), and then coupled with V_in through a bias-T. The normal input level V_in, along with the V_dd is produced by a semiconductor parameter analyzer (e.g., HP4145B). Then the coupled signal is directly injected to the test chip. The test chip should be designed and fabricated specially: the input and output of the inverter should have coplanar waveguides in ground-signal-ground (GSG) configuration. The VTC curve of the inverter is measured by the voltage monitor unit V_m1 in the semiconductor parameter analyzer. Through two filters (as shown in Fig. 5), the disturbed output logic voltage V_L and the high-frequency interference voltage V_H can be monitored respectively in V_m3 and V_m2.

Fig. 10.

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	Fig. 10. (color online) General experiment setup on effect of EMI on single CMOS inverter.

Considering the high complexity of the intentional electromagnetic environments, investigation on the influence of EMI frequency on the soft logic upset is valuable. Using the proposed parameter ΔV, we simulate L-to-C waveband EMI induced soft logic upset in CMOS inverter. Figure 11 illustrates the output ΔV varying with the injection power under different EMI frequencies, and the reported output logic voltages in experiment^[20] is also given for comparison. An apparent trend can be found that under 1-GHz-to-5-GHz EMI, lower interference frequencies tend to induce severer degeneration as shown by larger output ΔV, which is supported by the reported experimental results in Ref. [20]. In addition, Kim et al. conducted EMI experiments^[22] on single enhanced n-channel MOSFET, which can be considered as a part of the CMOS inverter, and the results revealed the same tendency as our simulations’. Moreover, in order to trace the physical understanding of the EMI frequency influence, device numerical simulation results of electron concentrations when V_in = 0.0 V are illustrated in Fig. 12. The condition of no EMI is plotted in Fig. 12(a) for comparison, figures 12(b) and 12(c) respectively illustrate the device internal electron concentrations under 1-GHz and 5-GHz EMI. The injection powers are both 24 dBm. Obvious electron inversion layers can be seen in these two figures, which confirms the existence of the soft logic upset. Furthermore, more substrate non-equilibrium electrons are found in Fig. 12(b), which is consistent with the conclusion in Fig. 11.

Fig. 11.

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	Fig. 11. (color online) Simulation results of (left) output ΔV and (right) experimental results of output voltage reported in Ref. [20] under EMI at frequencies ranging from 1 GHz to 5 GHz.

Fig. 12.

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	Fig. 12. (color online) Device simulation results of low level input electron concentrations under (a) no EMI, (b) 1-GHz and 24-dBm EMI, (c) 5-GHz and 24-dBm EMI. The inset shows the electron concentrations in NMOS channels.

Based on the mechanism explanation in Subsection 2.2, this frequency upset characteristic is attributed to the decrease of non-equilibrium carriers at higher frequencies. With the increase of the EMI frequency, the interference signal is no longer the slowing varying situation and the carriers change their directions too fast, thereby increasing the recombination possibility instead.

Investigation on the dependence between the device size and soft logic upset is conducted here. Half of size simulation device is established, compared with the primary CMOS inverter structure mentioned in Subsection 2.1. The shrinkage is based on the quasi-constant voltage reduction rule, which means that to maintain the normal operational function of the CMOS inverter, doping concentration in the device substrates should increase to 1.8 × 10¹⁷ cm³ (6 × 10¹⁶ cm³ in original size device) and the supply voltage should be adjusted to 2.5 V. Figure 13 shows the comparison between the interference degrees in original inverter and half the size of inverter under 3-dBm-to-32-dBm EMI when V_in = 0.0 V. Owing to having different V_dd values, the interference degree is represented by ΔV/V_dd. Obviously, half the size of CMOS inverter shows a more serious soft logic upset, whether the input is at a logic high level (see Fig. 13(a)) or at a low level (see Fig. 13(b)). To further confirm this conclusion, the electron concentration distributions of different device sizes are shown in Fig. 14. Figure 14(a) shows no EMI control group either, and figure 14(b) displays the original size simulation results under 24-dBm and 1-GHz EMI while figure 14(c) shows half the size of situation under the same interference. It can be indicated that the distribution trends of non-equilibrium electrons in inverters of different sizes are identical, which means that the mechanism of soft logic upset is not affected by device size. However, the value of non-equilibrium electron concentration is higher in half the size of device. This phenomenon is trigged by the fact that the inverters with smaller size are more inclined to accumulate the non-equilibrium carriers, which means that they are more likely to have soft logic upsets under EMI.

Fig. 13.

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	Fig. 13. (color online) 3-dBm-to-32-dBm EMI induced soft logic upsets in original and half the size of inverter at Vin = 3.3 V (a) and 0.0 V (b). The inset shows the results at an injection power of 3 dBm.

Fig. 14.

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	Fig. 14. (color online) Device simulation results of low level input electron concentrations at (a) original size and no EMI, (b) original size and 24-dBm EMI, (c) half size and 24-dBm EMI. The inset shows the electron concentrations in NMOS channels.